NXP Semiconductors K32 L2A Series, Reference Manual, Page: 54 / 1379

Table 3-3. Arm Cortex-M0+ parameter settings (continued)
Parameter Verilog name Value Description
System Tick Timer SYST 1 = Present Implements system tick timer (for CM4
compatibility)
DAP Target ID TARGETID 0 —
User/Privileged USER 1 = Present Implements processor operating modes
Vector Table Offset Register VTOR 1 = Present Implements relocation of exception vector
table
WIC Support WIC 1 = Present Implements WIC interface
WIC Requests WICLINES 34 Exact number of wake-up IRQs is 34
Watchpoints WPT 2 Implements two watchpoints
1. Documentation for this feature can be found at the Arm website
For details on the Arm Cortex-M0+ processor core, see the Arm website:
arm.com
.
3.4.3 Debug facilities
This device supports standard Arm 2-pin SWD debug port.
3.4.4 Buses, interconnects, and interfaces
The Arm Cortex-M0+ core has two bus interfaces:
• Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to
peripherals and all system memory, which includes flash memory and RAM
• Single 32-bit I/O port bus interfacing to the GPIO with 1-cycle loads and stores
3.4.5 System tick timer
The CLKSOURCE field in SysTick Control and Status register selects either the core
clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock (when
CLKSOURCE = 0). Because the timing reference is a variable frequency, the TENMS
field in the SysTick Calibration Value Register is always 0.
3.4.6 Caches
This device does not include any processor cache memories.
Core Modules
K32 L2A Reference Manual, Rev. 2, 01/2020
54 NXP Semiconductors