NXP Semiconductors K32 L2A Series, Reference Manual, Page: 350 / 1379

• If enabled, the Filter block will incur up to one bus clock additional latency penalty
on COUT due to the fact that COUT, which is crossing clock domain boundaries,
must be resynchronized to the bus clock.
• CR1[WE] and CR1[SE] are mutually exclusive.
16.2 Memory map/register definitions
CMP memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_E000 CMP Control Register 0 (CMP0_CR0) 8 R/W 00h 16.2.1/350
4006_E001 CMP Control Register 1 (CMP0_CR1) 8 R/W 00h 16.2.2/351
4006_E002 CMP Filter Period Register (CMP0_FPR) 8 R/W 00h 16.2.3/353
4006_E003 CMP Status and Control Register (CMP0_SCR) 8 R/W 00h 16.2.4/353
4006_E004 DAC Control Register (CMP0_DACCR) 8 R/W 00h 16.2.5/354
4006_E005 MUX Control Register (CMP0_MUXCR) 8 R/W 00h 16.2.6/355
400E_F000 CMP Control Register 0 (CMP1_CR0) 8 R/W 00h 16.2.1/350
400E_F001 CMP Control Register 1 (CMP1_CR1) 8 R/W 00h 16.2.2/351
400E_F002 CMP Filter Period Register (CMP1_FPR) 8 R/W 00h 16.2.3/353
400E_F003 CMP Status and Control Register (CMP1_SCR) 8 R/W 00h 16.2.4/353
400E_F004 DAC Control Register (CMP1_DACCR) 8 R/W 00h 16.2.5/354
400E_F005 MUX Control Register (CMP1_MUXCR) 8 R/W 00h 16.2.6/355
16.2.1 CMP Control Register 0 (CMPx_CR0)
Address: Base a 0h offset
Bit 7 6 5 4 3 2 1 0
Read 0
FILTER_CNT
0 0
HYSTCTR
Write
Reset 0 0 0 0 0 0 0 0
CMPx_CR0 field descriptions
Field Description
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6–4
FILTER_CNT
Filter Sample Count
Table continues on the next page...
Memory map/register definitions
K32 L2A Reference Manual, Rev. 2, 01/2020
350 NXP Semiconductors