NXP Semiconductors K32 L2A Series, Reference Manual, Page: 119 / 1379

Table 5-3. Detailed Clock Summary (continued)
Clock name Run mode - Clock
Frequency
VLPR mode -
Clock Frequency
HSRUN mode -
Clock Frequency
Clock source Clock can be
disabled when…
modes except for
partial stop modes.
DIVSLOW_CLK Up to 24 MHz DIVCORE_CLK
divide by 4 or more. Up to 24 MHz SCG When both CPUs
are in any stop
modes except for
partial stop modes.
SOSCDIV1_CLK,
SOSCDIV3_CLK Up to 48 MHz Up to 8 MHz Up to 48 MHz SCG If not being used by
any peripheral
and/or
DIVCORE_CLK or
feeding the PLL
SPLLDIV1_CLK,
SPLLDIV3_CLK Up to 72 MHz PLL disabled Up To 96 MHz SCG If not being used by
any peripheral
and/or
DIVCORE_CLK
FIRCDIV1_CLK,
FIRCDIV3_CLK Up to 60 MHz FIRC is disabled Up to 60 MHz SCG If not being used by
any peripheral
and/or
DIVCORE_CLK or
feeding the PLL
SIRCDIV1_CLK,
SIRCDIV3_CLK 8 MHz 8 MHz 8 MHz SCG If not being used by
any peripheral
and/or
DIVCORE_CLK
OSC32KCLK 30 kHz to 40 kHz 30-40 kHz low-
range crystal 30 kHz to 40 kHz external crystal
oscillator
connected to
EXTAL/XTAL or ext
clock on EXTAL pin If FIRC or SIRC is
being used by
SCG, and if no
peripherals are
using OSC32KCLK
LPO 1 kHz 1 kHz 1 kHz PMC's Low Power
Oscillator Can be disabled in
LLSx/VLLSx Stop
modes to save sub
uA current
consumption if not
used by LPTMRx
or other
peripherals.
5.11 Internal Clocking Requirements
The following requirements must be met when configuring the clocks for this device:
• The DIVCORE_CLK should not exceed 72MHz in normal RUN mode. The
DIVSLOW_CLK should not exceed 24 MHz for reliable flash memory operation
• The DIVCORE_CLK should not exceed 96MHz in High Speed RUN mode. The
DIVSLOW_CLK should not exceed 24 MHz for reliable flash memory operation.
Chapter 5 Clock Distribution
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 119