NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1127 / 1379

The stop modes range from:
• a stopped CPU, with all I/O, logic, and memory states retained, and certain
asynchronous mode peripherals operating
to:
• a powered down CPU, with only I/O and a small register file retained, very few
asynchronous mode peripherals operating, while the remainder of the MCU is
powered down.
The choice of stop mode depends upon the user's application, and how power usage and
state retention versus functional needs and recovery time may be traded off.
The various stop modes are selected by setting the appropriate fields in PMPROT and
PMCTRL. The selected stop mode is entered during the sleep-now or sleep-on-exit entry
with the SLEEPDEEP bit set in the System Control Register in the Arm core.
The available stop modes are:
• Normal Stop (STOP)
• Very-Low Power Stop (VLPS)
• Low-Leakage Stop (LLS)
• Very-Low-Leakage Stop (VLLSx)
44.4.5.1 STOP mode
STOP mode is entered via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in
the System Control Register in the Arm core.
The SCG module can be configured to leave the reference clocks running.
A module capable of providing an asynchronous interrupt to the device takes the device
out of STOP mode and returns the device to normal RUN mode. Refer to the device's
Power Management chapter for peripheral, I/O, and memory operation in STOP mode.
When an interrupt request occurs, the CPU exits STOP mode and resumes processing,
beginning with the stacking operations leading to the interrupt service routine.
A system reset will cause an exit from STOP mode, returning the device to normal RUN
mode via an MCU reset.
A system reset will cause an exit from STOP mode, temporarily returning the device to
RUN mode before transitioning into VLPR during the MCU reset flow.
Chapter 44 System Mode Controller (SMC)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1127