NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1324 / 1379

51.4.23 Endpoint Control register (USBx_ENDPTn)
Contains the endpoint control bits for each of the 16 endpoints available within the USB
module for a decoded address. The format for these registers is shown in the following
figure. Endpoint 0 (ENDPT0) is associated with control pipe 0, which is required for all
USB functions. Therefore, after a USBRST interrupt occurs the processor core should set
ENDPT0 to contain 0x0D.
In Host mode ENDPT0 is used to determine the handshake, retry and low speed
characteristics of the host transfer. For Control, Bulk and Interrupt transfers, the
EPHSHK bit should be 1. For Isochronous transfers it should be 0. Common values to
use for ENDPT0 in host mode are 0x4D for Control, Bulk, and Interrupt transfers, and
0x4C for Isochronous transfers.
The three bits EPCTLDIS, EPRXEN, and EPTXEN define if an endpoint is enabled and
define the direction of the endpoint. The endpoint enable/direction control is defined in
the following table.
Table 51-7. Endpoint enable and direction control
EPCTLDIS EPRXEN EPTXEN Endpoint enable/direction
control
X 0 0 Disable endpoint
X 0 1 Enable endpoint for Tx
transfers only
X 1 0 Enable endpoint for Rx
transfers only
1 1 1 Enable endpoint for Rx and
Tx transfers
0 1 1 Enable Endpoint for RX and
TX as well as control
(SETUP) transfers.
Address: 4005_5000h base + C0h (4d × i), where i=0d to 15d
Bit 7 6 5 4 3 2 1 0
Read HOSTWOH
UB
RETRYDIS
0
EPCTLDIS EPRXEN EPTXEN EPSTALL EPHSHK
Write
Reset
0 0 0 0 0 0 0 0
USBx_ENDPTn field descriptions
Field Description
7
HOSTWOHUB
Host without a hub This is a Host mode only field and is present in the control register for endpoint 0
(ENDPT0) only.
Table continues on the next page...
Memory map/Register definitions
K32 L2A Reference Manual, Rev. 2, 01/2020
1324 NXP Semiconductors