NXP Semiconductors K32 L2A Series, Reference Manual, Page: 836 / 1379

31.3.1 Baud rate generation
A 13-bit modulus counter in the baud rate generator derive the baud rate for both the
receiver and the transmitter. The value from 1 to 8191 written to SBR[12:0] determines
the baud clock divisor for the asynchronous LPUART baud clock. The SBR bits are in
the LPUART baud rate registers, BDH and BDL. The baud rate clock drives the receiver,
while the transmitter is driven by the baud rate clock divided by the over sampling ratio.
Depending on the over sampling ratio, the receiver has an acquisition rate of 4 to 32
samples per bit time.
Rx Sampling Clock
[(OSR+1) × Baud Rate]
Baud Rate =
Modulo Divide By
(1 through 8191)
LPUART ASYNCH
Module Clock
LPUART ASYNCH Module Clock
Divide By
(OSR+1)
OSR
SBR[12:0]
Baud Rate Generator
Off If [SBR12:SBR0] =0
SBR[12:0] × (OSR+1)
Tx Baud Rate
Figure 31-3. LPUART baud rate generation
Baud rate generation is subject to two sources of error:
• Integer division of the asynchronous LPUART baud clock may not give the exact
target frequency.
• Synchronization with the asynchronous LPUART baud clock can cause phase shift.
31.3.2 Transmitter functional description
This section describes the overall block diagram for the LPUART transmitter, as well as
specialized functions for sending break and idle characters.
The transmitter output (LPUART_TX) idle state defaults to logic high, CTRL[TXINV] is
cleared following reset. The transmitter output is inverted by setting CTRL[TXINV]. The
transmitter is enabled by setting the CTRL[TE] bit. This queues a preamble character that
is one full character frame of the idle state. The transmitter then remains idle until data is
available in the transmit data buffer. Programs store data into the transmit data buffer by
writing to the LPUART data register.
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
836 NXP Semiconductors