NXP Semiconductors K32 L2A Series, Reference Manual, Page: 577 / 1379

Table 22-5. UART Receiver Configuration
Register Value Comments
read using interrupt or DMA request.
Can support MSB first transfer by
reading from SHIFTBUFBIS[7:0] register
instead.
The UART Receiver with RTS configuration uses a 2nd Timer to generate the RTS
output. The RTS will assert when the start bit is detected and negate when the data is read
from the shifter buffer register. No start bit will be detected while the RTS is asserted, the
received data is simply ignored.
Table 22-6. UART Receiver with RTS Configuration
Register Value Comments
SHIFTCFGn 0x0000_0032 Configure start bit of 0 and stop bit of 1.
SHIFTCTLn 0x0080_0001 Configure receive using Timer 0 on
negedge of clock with input data on Pin
0. Can invert input data by setting
PINPOL.
TIMCMPn 0x0000_0F01 Configure 8-bit transfer with baud rate of
divide by 4 of the FlexIO clock. Set
TIMCMP[15:8] = (number of bits x 2) - 1.
Set TIMCMP[7:0] = (baud rate divider /
2) - 1.
TIMCFGn 0x0204_2522 Configure start bit, stop bit, enable on
pin posedge with trigger low and disable
on compare. Enable resynchronization
to received data with TIMOUT=0x2 and
TIMRST=0x4.
TIMCTLn 0x03C0_0081 Configure dual 8-bit counter using
inverted Pin 0 input. Trigger is internal
using inverted Pin 1 input.
TIMCMP(n+1) 0x0000_FFFF Never compare.
TIMCFG(n+1) 0x0030_6100 Enable on Timer N enable and disable
on trigger falling edge. Decrement on
trigger to ensure no compare.
TIMCTL(n+1) 0x0143_0083 Configure 16-bit counter and output on
Pin 1. Trigger is internal using Shifter 0
flag.
SHIFTBUFn Data to receive Received data can be read from
SHIFTBUFBYS[7:0], use the Shifter
Status Flag to indicate when data can be
read using interrupt or DMA request.
Can support MSB first transfer by
reading from SHIFTBUFBIS[7:0] register
instead.
Chapter 22 Flexible I/O (FlexIO)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 577