NXP Semiconductors K32 L2A Series, Reference Manual, Page: 780 / 1379

29.2.14 Transmit Command Register (LPSPIx_TCR)
Writes to either the Transmit Command Register or Transmit Data Register will push the
data into the transmit FIFO in the order they are written. Command Register writes will
be tagged and cause the command register to update once that entry reaches the top of the
FIFO. This allows changes to the command word and the transmit data itself to be
interleaved. Changing the command word will cause all subsequent SPI bus transfer to be
performed using the new command word.
In master mode, writing a new command word does not initiate a new transfer, unless
TXMSK is set. Transfers are initiated by transmit data in the transmit FIFO, or a new
command word with TXMSK set. Hardware will clear TXMSK when the LPSPI_PCS
negates.
In master mode if the command word is changed before an existing frame has completed,
then the existing frame will terminate and the command word will then update. The
command word can be changed during a continuous transfer, provided CONTC of the
new command word is set and the command word is written on a frame size boundary.
In slave mode, the command word should be changed only when the LPSPI is idle and
there is no SPI bus transfer.
Reading the Transmit Command Register will return the current state of the command
register.
Address: Base a 60h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CPOL CPHA
PRESCALE
0
PCS LSBF
BYSW
CONT
CONTC RXMSK
TXMSK
WIDTH
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
FRAMESZ
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
LPSPIx_TCR field descriptions
Field Description
31
CPOL
Clock Polarity
This field is only updated between frames.
Table continues on the next page...
Memory Map and Registers
K32 L2A Reference Manual, Rev. 2, 01/2020
780 NXP Semiconductors