NXP Semiconductors K32 L2A Series, Reference Manual, Page: 154 / 1379

9.4.2 MDM-AP Status Register
Table 9-5. MDM-AP Status register assignments
Bit Name Description
0 Flash Mass Erase Acknowledge The Flash Mass Erase Acknowledge bit is cleared after a Power-On Reset
(POR). The Flash Mass Erase Acknowledge is set after Flash control logic
has started the mass erase operation.
When mass erase is disabled (via MEEN), an erase request due to setting
of Flash Mass Erase in Progress bit is not acknowledged.
1 Flash Ready Indicates Flash has been initialized and the debugger can be configured,
even if the system is continuing to be held in reset by the debugger.
2 System Security Indicates the security state. When secure, the debugger does not have
access to the system bus or any memory-mapped peripherals. This bit
indicates when the part is locked and no system bus access is possible.
3 System Reset Indicates the system reset state.
0 System is in reset.
1 System is not in reset.
4 Reserved
5 Mass Erase Enable Indicates if the MCU can be mass erased or not
0 Mass erase is disabled.
1 Mass erase is enabled .
6 Backdoor Access Key Enable Indicates if the MCU has the backdoor access key enabled.
0 Disabled
1 Enabled
7 LP Enabled Decode of SMC_PMCTRL[STOPM] field to indicate that VLPS, LLS, or
VLLSx are the selected power mode for the next time that the Arm Core
enters Deep Sleep.
0 Low Power Stop Mode is not enabled.
1 Low Power Stop Mode is enabled.
This bit is intended to be used for debug operations in which Run to VLPS
is attempted. Per the debug definition, the system actually enters the Stop
state. A debugger should interpret a deep sleep indication (with
SLEEPDEEP and SLEEPING asserted), in conjunction with LP Enabled
bit asserted, as the debugger-VLPS status indication.
8 Very Low Power Mode Indicates that the current power mode is VLPx. This bit is not ‘sticky’ and
should always represent whether VLPx is enabled or not.
This bit is used to throttle SWD_CLK frequency up/down.
9 LLS Mode Exit Indicates an exit from LLS mode has occurred. The debugger will lose
communication while the system is in LLS (including access to this
register). After communication is re-established, this bit indicates that the
system had been in LLS. Because the debug modules held their state
during LLS, they do not need to be reconfigured.
This bit is set during the LLS recovery sequence. The LLS Mode Exit bit is
held until the debugger has had a chance to recognize that LLS was
exited, and is cleared by a write of 1 to the LLS, VLLSx Status
Acknowledge bit in MDM AP Control register.
Table continues on the next page...
SWD status and control registers
K32 L2A Reference Manual, Rev. 2, 01/2020
154 NXP Semiconductors