NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1067 / 1379

SCG_HCCR field descriptions (continued)
Field Description
1000 Divide-by-9
1001 Divide-by-10
1010 Divide-by-11
1011 Divide-by-12
1100 Divide-by-13
1101 Divide-by-14
1110 Divide-by-15
1111 Divide-by-16
15–12
Reserved
This field is reserved. Software should write 0 to these bits to maintain compatibility.
This field is reserved.
11–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
DIVSLOW Slow Clock Divide Ratio
0000 Divide-by-1
0001 Divide-by-2
0010 Divide-by-3
0011 Divide-by-4
0100 Divide-by-5
0101 Divide-by-6
0110 Divide-by-7
0111 Divide-by-8
1000 Divide-by-9
1001 Divide-by-10
1010 Divide-by-11
1011 Divide-by-12
1100 Divide-by-13
1101 Divide-by-14
1110 Divide-by-15
1111 Divide-by-16
42.2.7 SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG)
This register controls which SCG clock source is selected to be ported out to the
CLKOUT pin.
Address: 4007_B000h base + 20h offset = 4007_B020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLKOUTSEL
0
W
Reset
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 42 System Clock Generator (SCG)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1067