NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1053 / 1379

Crystal compensation can be supported by using firmware and crystal characteristics to
determine the compensation amount. Temperature compensation can be supported by
firmware that periodically measures the external temperature via ADC and updates the
compensation register based on a look-up table that specifies the change in crystal
frequency over temperature.
The compensation logic alters the number of 32.768 kHz clock cycles it takes for the
prescaler register to overflow and increment the time seconds counter. The time
compensation value is used to adjust the number of clock cycles between -127 and +128.
Cycles are added or subtracted from the prescaler register when the prescaler register
equals 0x3FFF and then increments. The compensation interval is used to adjust the
frequency at which the time compensation value is used, that is, from once a second to
once every 256 seconds.
Updates to the time compensation register will not take effect until the next time the time
seconds register increments and provided the previous compensation interval has expired.
When the compensation interval is set to other than once a second then the compensation
is applied in the first second interval and the remaining second intervals receive no
compensation.
Compensation is disabled by configuring the time compensation register to zero.
When the prescaler is configured to increment using the 1 kHz LPO, the effective
compensation value is divided by 32 and can only adjust the number of clock cycles
between -4 and +3.
41.3.4 Time alarm
The Time Alarm register (TAR), SR[TAF], and IER[TAIE] allow the RTC to generate an
interrupt at a predefined time. The 32-bit TAR is compared with the 32-bit Time Seconds
register (TSR) each time it increments. SR[TAF] will set when TAR equals TSR and
TSR increments.
SR[TAF] is cleared by writing TAR. This will usually be the next alarm value, although
writing a value that is less than TSR, such as 0, will prevent SR[TAF] from setting again.
SR[TAF] cannot otherwise be disabled, although the interrupt it generates is enabled or
disabled by IER[TAIE].
Chapter 41 Real Time Clock (RTC)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1053