NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1029 / 1379

Chapter 40
General-Purpose Input/Output (GPIO)
40.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances, see the chip configuration information.
The general-purpose input and output (GPIO) module is accessible via the peripheral bus
and also communicates to the processor core via a zero wait state interface (IOPORT) for
maximum pin performance. The GPIO registers support 8-bit, 16-bit or 32-bit accesses.
The GPIO data direction and output data registers control the direction and output data of
each pin when the pin is configured for the GPIO function. The GPIO input data register
displays the logic value on each pin when the pin is configured for any digital function,
provided the corresponding Port Control and Interrupt module for that pin is enabled.
Efficient bit manipulation of the general-purpose outputs is supported through the
addition of set, clear, and toggle write-only registers for each port output data register.
40.1.1 Features
Features of the GPIO module include:
• Port Data Input register visible in all digital pin-multiplexing modes
• Port Data Output register with corresponding set/clear/toggle registers
• Port Data Direction register
• Zero wait state access to GPIO registers through IOPORT
NOTE
The GPIO module is clocked by system clock.
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1029