NXP Semiconductors K32 L2A Series, Reference Manual, Page: 756 / 1379

28.3.9 Current Timer Value (LPITx_CVALn)
These registers indicate the current timer counter value.
NOTE
While the timer is running, CVALn register reads may not
return the real value.
Address: 4003_0000h base + 24h (16d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TMR_CUR_VAL
W
Reset
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
LPITx_CVALn field descriptions
Field Description
TMR_CUR_VAL Current Timer Value
Represents the current timer value, if the timer is enabled.
28.3.10 Timer Control Register (LPITx_TCTRLn)
These registers contain the control bits for each timer channel
Address: 4003_0000h base + 28h (16d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
TRG_SEL
TRG_
SRC
0
TROT TSOI TSOT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
MODE
CHAIN
T_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory Map and Registers
K32 L2A Reference Manual, Rev. 2, 01/2020
756 NXP Semiconductors