NXP Semiconductors K32 L2A Series, Reference Manual, Page: 758 / 1379

LPITx_TCTRLn field descriptions (continued)
Field Description
3–2
MODE
Timer Operation Mode
Configures the Channel Timer Mode of Operation. The mode bits control how the timer decrements. See
Functional Description for more details.
00 32-bit Periodic Counter
01 Dual 16-bit Periodic Counter
10 32-bit Trigger Accumulator
11 32-bit Trigger Input Capture
1
CHAIN
Chain Channel
When enabled, timer channel will decrement when channel N-1 trigger asserts. Channel 0 cannot be
chained.
0 Channel Chaining is disabled. Channel Timer runs independently.
1 Channel Chaining is enabled. Timer decrements on previous channel's timeout
0
T_EN
Timer Enable
Enables or disables the Timer Channel
0 Timer Channel is disabled
1 Timer Channel is enabled
28.4 Functional description
28.4.1 Initialization
The following steps can be used to initialize the LPIT module
• Enable the protocol clock by setting the M_CEN bit in the MCR register.
NOTE
Writing to certain registers while M_CEN = 0 will lead to
assertion of transfer error for that bus access. These
registers are MSR, SETTEN, CLRTEN, TVAL, and
TCTRL. Writing to CVAL and Reserved registers will
generate a transfer error irrespective of M_CEN bit value.
Reads to these registers can happen irrespective of M_CEN
bit value.
• Wait for 4 protocol clock cycles to allow time for clock synchronization and reset de-
assertion.
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
758 NXP Semiconductors