NXP Semiconductors K32 L2A Series, Reference Manual, Page: 229 / 1379

Chapter 13
Bit Manipulation Engine2 (BME2)
13.1 Introduction
The Bit Manipulation Engine with the BME2 definition (BME2) provides hardware
support for atomic read-modify-write memory operations to the first 1 Mbyte of slave
peripheral address space in Cortex-M based microcontrollers. The second generation
BME2 provides similar atomic read-modify-write capabilities to a larger peripheral
address space versus the original implementation. The BME terminology is meant to be
equivalent to BME2 throughout this chapter.
This architectural capability is also known as "decorated storage" as it defines a
mechanism for providing additional semantics for load and store operations to memory-
mapped peripherals beyond just the reading and writing of data values to the addressed
memory locations. In the BME definition, the "decoration", that is, the additional
semantic information, is encoded into the peripheral address used to reference the
memory. The BME2 definition supports up to two AIPS bus controllers, each capable of
addressing 512 KB of peripheral address space. BME2 supports an 8-bit or less data field
width for bit field inserts and extracts, regardless of reference size. All other BME2
operations are exactly the same as the original definition.
By combining the basic load and store instructions of the Arm Cortex-M instruction set
architecture (v6M, v7M) with the concept of decorated storage provided by BME, the
resulting implementation provides a robust and efficient read-modify-write capability.
The resulting architectural capability defined by this core platform function is targeted at
the manipulation of n-bit fields in peripheral registers and is consistent with I/O hardware
addressing in the Embedded C standard. For most BME commands, a single core read or
write bus cycle is converted into an atomic read-modify-write, that is, an indivisible "read
followed by a write" bus sequence.
BME decorated references are only available on system bus transactions generated by the
processor core and DMA, and targeted at the 1024 KB peripheral address space based at
0x4000_0000. The decoration semantic is embedded into address bits[28:20], creating a
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