NXP Semiconductors K32 L2A Series, Reference Manual, Page: 237 / 1379

The decorated BFI write operation is defined in the following pseudo-code as:
iobfi<sz>(accessAddress, wdata) // decorated bit field insert
tmp = mem[accessAddress & 0xE00FFFFF, size] // memory read
mask = ((1 << (w+1)) - 1) << b // generate bit mask
tmp = tmp & ~mask // modify
| wdata & mask
mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write
The write data operand (wdata) associated with the store instruction contains the bit field
to be inserted. It must be properly aligned within the right-aligned container, that is,
within the lower 8 bits for a byte operation, the lower 16 bits for a halfword, or the entire
32 bits for a word operation.
To illustrate, consider the following example of the insertion of the 3-bit field "xyz" into
an 8-bit memory container, initially set to "abcd_efgh". For all cases, w is 2, signaling a
bit field width of 3.
if b = 0 and the decorated store (strb) Rt register[7:0] = ----_-xyz,
then destination is "abcd_exyz"
if b = 1 and the decorated store (strb) Rt register[7:0] = ----_xyz-,
then destination is "abcd_xyzh"
if b = 2 and the decorated store (strb) Rt register[7:0] = ---x_yz--,
then destination is "abcx_yzgh"
if b = 3 and the decorated store (strb) Rt register[7:0] = --xy_z---,
then destination is "abxy_zfgh"
if b = 4 and the decorated store (strb) Rt register[7:0] = -xyz_----,
then destination is "axyz_efgh"
if b = 5 and the decorated store (strb) Rt register[7:0] = xyz-_----,
then destination is "xyzd_efgh"
if b = 6 and the decorated store (strb) Rt register[7:0] = yz--_----,
then destination is "yzcd_efgh"
if b = 7 and the decorated store (strb) Rt register[7:0] = z---_----,
then destination is "zbcd_efgh"
Note from the example, when the starting bit position plus the field width exceeds the
container size, only part of the source bit field is inserted into the destination memory
location. Stated differently, if (b + w+1) > container_width, only the low-order
"container_width - b" bits are actually inserted.
The cycle-by-cycle BME operations are detailed in the following table.
Table 13-4. Cycle definitions of decorated store: bit field insert
Pipeline stage Cycle
x x+1 x+2
BME AHB_ap Forward addr to memory;
Decode decoration; Convert
master_wt to slave_rd;
Capture address, attributes Recirculate captured addr +
attr to memory as slave_wt <next>
BME AHB_dp <previous> Perform memory read; Form
bit mask; Form bitwise
((mask) ? wdata : rdata)) and
capture destination data in
register Perform write sending
registered data to memory
Chapter 13 Bit Manipulation Engine2 (BME2)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 237