NXP Semiconductors K32 L2A Series, Reference Manual, Page: 714 / 1379

27.2.13 Master Clock Configuration Register 1 (LPI2Cx_MCCR1)
The MCCR1 cannot be changed when the I2C master is enabled and is used for high
speed mode transfers. The separate clock configuration for high speed mode allows
arbitration to take place in Fast mode (with timing configured by MCCR0), before
switching to high speed mode (with timing configured by MCCR1).
Address: Base a 50h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DATAVD
0
SETHOLD
0
CLKHI
0
CLKLO
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPI2Cx_MCCR1 field descriptions
Field Description
31–30
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
29–24
DATAVD
Data Valid Delay
Minimum number of cycles (minus one) that is used as the data hold time for SDA. Must be configured
less than the minimum SCL low period.
23–22
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
21–16
SETHOLD
Setup Hold Delay
Minimum number of cycles (minus one) that is used by the master as the setup and hold time for a
(repeated) START condition and setup time for a STOP condition. The setup time is extended by the time
it takes to detect a rising edge on the external SCL pin. Ignoring any additional board delay due to external
loading, this is equal to (2 + FILTSCL) / 2^PRESCALE cycles.
15–14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13–8
CLKHI
Clock High Period
Minimum number of cycles (minus one) that the SCL clock is driven high by the master. The SCL high
time is extended by the time it takes to detect a rising edge on the external SCL pin. Ignoring any
additional board delay due to external loading, this is equal to (2 + FILTSCL) / 2^PRESCALE cycles.
7–6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
CLKLO Clock Low Period
Minimum number of cycles (minus one) that the SCL clock is driven low by the master. This value is also
used for the minimum bus free time between a STOP and a START condition.
Memory Map and Registers
K32 L2A Reference Manual, Rev. 2, 01/2020
714 NXP Semiconductors