NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1309 / 1379

51.4.5 OTG Interrupt Status register (USBx_OTGISTAT)
Records changes to the state of the one-millisecond timer and line state stable logic.
Software can read this register to determine the event that triggers an interrupt. Only bits
that have changed since the last software read are set. Writing a one to a bit clears the
associated interrupt.
Address: 4005_5000h base + 10h offset = 4005_5010h
Bit 7 6 5 4 3 2 1 0
Read Reserved ONEMSEC
LINE_
STATE_
CHG
0 Reserved Reserved 0 Reserved
Write w1c w1c
w1c
w1c w1c w1c
Reset 0 0 0 0 0 0 0 0
USBx_OTGISTAT field descriptions
Field Description
7
Reserved
This field is reserved.
Software must not change the value of this bitfield.
6
ONEMSEC
This bit is set when the 1 millisecond timer expires. This bit stays asserted until cleared by software. The
interrupt must be serviced every millisecond to avoid losing 1msec counts.
5
LINE_STATE_
CHG
This interrupt is set when the USB line state (CTL[SE0] and CTL[JSTATE] bits) are stable without change
for 1 millisecond, and the value of the line state is different from the last time when the line state was
stable. It is set on transitions between SE0 and J-state, SE0 and K-state, and J-state and K-state.
Changes in J-state while SE0 is true do not cause an interrupt. This interrupt can be used in detecting
Reset, Resume, Connect, and Data Line Pulse signaling.
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
Reserved
This field is reserved.
Software must not change the value of this bitfield.
2
Reserved
This field is reserved.
Software must not change the value of this bitfield.
1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
Reserved
This field is reserved.
Software must not change the value of this bitfield.
Chapter 51 Universal Serial Bus Full Speed OTG Controller (USBFSOTG)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1309