NXP Semiconductors K32 L2A Series, Reference Manual, Page: 462 / 1379

• Internal SRAM can be accessed with zero wait-states when viewed from the system
bus data phase
• All internal peripheral bus reads require two wait-states, and internal peripheral bus
writes three wait-states, when viewed from the system bus data phase
• All internal peripheral bus accesses are 32-bits in size
NOTE
All architectures will not meet the assumptions listed above.
See the SRAM configuration section for more information.
This table compares peak transfer rates based on different possible system speeds.
Specific chips/devices may not support all system speeds listed.
Table 20-4. eDMA peak transfer rates (Mbytes/sec)
System Speed, Width
Internal SRAM-to-
Internal SRAM
32 bit internal peripheral
bus-to-Internal SRAM
Internal SRAM-to-32 bit
internal peripheral bus
48 MHz, 32 bit 96.0 48.0 38.4
66.7 MHz, 32 bit 133.3 66.7 53.3
83.3 MHz, 32 bit 166.7 83.3 66.7
100.0 MHz, 32 bit 200.0 100.0 80.0
133.3 MHz, 32 bit 266.7 133.3 106.7
150.0 MHz, 32 bit 300.0 150.0 120.0
Internal-SRAM-to-internal-SRAM transfers occur at the core's datapath width. For all
transfers involving the internal peripheral bus, 32-bit transfer sizes are used. In all cases,
the transfer rate includes the time to read the source plus the time to write the destination.
20.4.4.2 Peak request rates
The second performance metric is a measure of the number of DMA requests that can be
serviced in a given amount of time. For this metric, assume that the peripheral request
causes the channel to move a single internal peripheral bus-mapped operand to/from
internal SRAM. The same timing assumptions used in the previous example apply to this
calculation. In particular, this metric also reflects the time required to activate the
channel.
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
462 NXP Semiconductors