NXP Semiconductors K32 L2A Series, Reference Manual, Page: 739 / 1379

• During 8th clock pulse of address byte or slave-receive transfer and transmit ACK
flag is set. This is disabled in high speed mode.
• Clock stretching can also be extended for CLKHOLD cycles to allow additional
setup time to sample the SDA pin externally. This is disabled in high speed mode.
Unless extended by the CLKHOLD configuration, clock stretching will extend for one
peripheral bus clock cycle after SDA updates when clock stretching is enabled.
27.3.3.4 Timing Parameters
The LPI2C slave can configure the following timing parameters, these parameters are
disabled when SCR[FILTEN] is clear, when SCR[FILTDZ] is set in Doze mode, and
when LPI2C slave detects high speed mode. When disabled, the LPI2C slave is clocked
directly from the I2C bus and may not satisfy all timing requirements of the I2C
specification (such as SDA minimum hold time in Standard/Fast mode).
• SDA data valid time from SCL negation to SDA update.
• SCL hold time when clock stretching is enabled to increase setup time when
sampling SDA externally.
• SCL glitch filter time.
• SDA glitch filter time.
The LPI2C slave imposes the following restrictions on the timing parameters.
• FILTSDA must be configured to greater than or equal to FILTSCL (unless
compensating for board level skew between SDA and SCL).
• DATAVD must be configured less than the minimum SCL low period.
27.3.3.5 Error Conditions
The LPI2C slave can detect the following error conditions.
• Bit error flag will set when the LPI2C slave is driving SDA, but samples a different
value than what is expected.
• FIFO error flag will set due to a transmit data underrun or a receive data overrun.
Clock stretching can be enabled to eliminate the possibility of underrun and overrun
occurring.
• FIFO error flag will also set due to an address overrun when RXCFG is set,
otherwise an address overrun is not flagged. Clock stretching can be enabled to
eliminate the possibility of overrun occurring.
Chapter 27 Low Power Inter-Integrated Circuit (LPI2C)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 739