NXP Semiconductors K32 L2A Series, Reference Manual, Page: 334 / 1379

Value of bits 31, 20, and 9 Number of commands included
100 1
110 2
111 3
All other combinations of bits 31, 20, and 9 are illegal and generate an error termination.
15.6.3 CAU commands
The CAU supports the commands shown in the following table. All other encodings are
reserved. The CASR[IC] bit is set if an undefined command is issued. A specific illegal
command (ILL) is defined to allow software self-checking. Reserved commands must not
be issued so as to ensure compatibility with future implementations.
The CMD field specifies the 9-bit CAU opcode for the operation command.
See Assembler equate values for a set of assembly constants used in the command
descriptions here. If supported by the assembler, macros can also be created for each
instruction. The value CAx should be interpreted as any CAU register (CASR, CAA, and
CAn).
Table 15-2. CAU commands
Type
Command
name
Description
CMD
Operation
8 7 6 5 4 3 2 1 0
Direct load CNOP No Operation 0x000 —
Indirect load LDR Load Reg 0x01 CAx Op1
→
CAx
Indirect store STR Store Reg 0x02 CAx CAx
→
Result
Indirect load ADR Add 0x03 CAx CAx + Op1
→
CAx
Indirect load RADR Reverse and Add 0x04 CAx CAx + ByteRev(Op1)
→
CAx
Direct load ADRA Add Reg to Acc 0x05 CAx CAx + CAA
→
CAA
Indirect load XOR Exclusive Or 0x06 CAx CAx ^ Op1
→
CAx
Indirect load ROTL Rotate Left 0x07 CAx (CAx <<< (Op1 % 32)) | (CAx
>>> (32 - (Op1 % 32)))
→
CAx
Direct load MVRA Move Reg to Acc 0x08 CAx CAx
→
CAA
Direct load MVAR Move Acc to Reg 0x09 CAx CAA
→
CAx
Direct load AESS AES Sub Bytes 0x0A CAx SubBytes(CAx)
→
CAx
Direct load AESIS AES Inv Sub Bytes 0x0B CAx InvSubBytes(CAx)
→
CAx
Indirect load AESC AES Column Op 0x0C CAx MixColumns(CAx)^Op1
→
CAx
Indirect load AESIC AES Inv Column Op 0x0D CAx InvMixColumns(CAx^Op1)
→
CAx
Table continues on the next page...
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
334 NXP Semiconductors