NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1129 / 1379

NOTE
The LLWU interrupt must not be masked by the interrupt
controller to avoid a scenario where the system does not fully
exit Stop mode on an LLS recovery.
An asserted RESET pin will cause an exit from LLS mode, returning the device to
normal RUN mode. When LLS is exiting via the RESET pin, RCM_SRS[PIN] and
RCM_SRS[WAKEUP] are set.
An asserted RESET pin will cause an exit from LLS mode, temporarily returning the
device to normal RUN mode before transitioning into VLPR during the MCU reset flow.
When LLS is exiting via the RESET pin, RCM_SRS[PIN] and RCM_SRS[WAKEUP]
are set.
44.4.5.4 Very-Low-Leakage Stop (VLLSx) modes
This device contains these very low leakage modes:
• VLLS3
• VLLS2
• VLLS1
• VLLS0
VLLSx is often used in this document to refer to all of these modes.
All VLLSx modes can be entered from normal RUN or VLPR modes.
The MCU enters the configured VLLS mode if:
• In Sleep-Now or Sleep-On-Exit mode, the SLEEPDEEP bit is set in the System
Control Register in the Arm core, and
• The device is configured as shown in Table 44-2 .
In VLLS, the on-chip voltage regulator is in its stop-regulation state while most digital
logic is powered off.
Before entering VLLS mode, the user should configure the Low-Leakage Wake-up
(LLWU) module to enable the desired wakeup sources. The available wake-up sources in
VLLS are detailed in the chip configuration details for this device.
After wakeup from VLLS, the device returns to normal RUN mode with a pending
LLWU interrupt. If VLLS was entered from VLPR mode, then the MCU will begin
VLPR entry shortly after wakeup. In the LLWU interrupt service routine (ISR), the user
can poll the LLWU module wake-up flags to determine the source of the wake-up.
Chapter 44 System Mode Controller (SMC)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1129