NXP Semiconductors K32 L2A Series, Reference Manual, Page: 296 / 1379

Fetch
Response
Yes
Yes
payload length
part from target
(2 bytes)
CRC checksum
from target
Payload length
less than supported
length?
Yes
payload data
from target
No
Set payload length
to maximum
supported length
No
No
Reached
maximum
Report a timeout
Yes
End
No
(2 bytes)
Read 1 byte
from target
0x5A
received?
0xA4
received?
Read 1 byte
from target
retries?
error (End)
Read
Read
Read
Figure 14-23. Host reads response from target via LPI2C
14.4.2 LPSPI Peripheral
The Kinetis Bootloader in ROM supports loading data into flash via the LPSPI
peripheral, where the LPSPI peripheral serves as a LPSPI slave.
Maximum supported baud rate of LPSPI depends on the clock configuration fields in the
Bootloader Configuration Area (BCA) shown in
Table 14-3 . The typical supported baud
rate is 400 kbps with the factory settings. The actual baud rate is lower or higher than 400
kbps, depending on the actual value of the clockFlags and clockDivider fields in the
BCA.
The LPSPI peripheral uses the following bus attributes:
• Clock Phase = 1 (Second Edge)
• Clock Polarity = 1 (Active Low)
Because the LPSPI peripheral in ROM serves as a LPSPI slave device, each transfer
should be started by the host, and each outgoing packet should be fetched by the host.
The transfer on LPSPI is slightly different from I2C:
• Host will receive 1 byte after it sends out any byte.
• Received bytes should be ignored when host is sending out bytes to target
• Host starts reading bytes by sending 0x00s to target
• The byte 0x00 will be sent as response to host if target is under the following
conditions:
Peripherals Supported
K32 L2A Reference Manual, Rev. 2, 01/2020
296 NXP Semiconductors