NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1011 / 1379

The PORT module generates a single DMA request that asserts when the interrupt status
flag is set for any enabled DMA request in that port. The DMA request negates after the
DMA transfer is completed, because that clears the interrupt status flags for all enabled
DMA requests.
During Stop mode, the interrupt status flag for any enabled interrupt is asynchronously
set if the required level or edge is detected. This also generates an asynchronous wake-up
signal to exit the Low-Power mode.
The PORT module generates a single peripheral trigger output that asserts if any pin
configured for active high trigger is logic one, or any pin triggered for active low trigger
is logic zero. The peripheral trigger output asynchronously updates from the value on the
configured pins or at the output of the digital input filter, if the digital input digital filter
is enabled.
38.6.5 Digital filter
The digital filter capabilities of the PORT module are available in all digital Pin Muxing
modes if the PORT module is enabled.
The clock used for all digital filters within one port can be configured between the bus
clock or the LPO clock. This selection must be changed only when all digital filters for
that port are disabled. If the digital filters for a port are configured to use the bus clock,
then the digital filters are bypassed for the duration of Stop mode. While the digital filters
are bypassed, the output of each digital filter always equals the input pin, but the internal
state of the digital filters remains static and does not update due to any change on the
input pin.
The filter width in clock size is the same for all enabled digital filters within one port and
must be changed only when all digital filters for that port are disabled.
The output of each digital filter is logic zero after system reset and whenever a digital
filter is disabled. After a digital filter is enabled, the input is synchronized to the filter
clock, either the bus clock or the LPO clock. If the synchronized input and the output of
the digital filter remain different for a number of filter clock cycles equal to the filter
width register configuration, then the output of the digital filter updates to equal the
synchronized filter input.
The maximum latency through a digital filter equals three filter clock cycles plus the
filter width configuration register.
Chapter 38 Port Control and Interrupts (PORT)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1011