NXP Semiconductors K32 L2A Series, Reference Manual, Page: 323 / 1379

Chapter 15
Cryptographic Acceleration Unit (CAU)
15.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances, see the chip configuration information.
The memory-mapped Cryptographic Acceleration Unit (CAU) is a coprocessor that is
connected to the processor's Private Peripheral Bus (PPB). It supports the hardware
implementation of a set of specialized operations to improve the throughput of software-
based security encryption/decryption operations and message digest functions.
The CAU supports acceleration of the DES, 3DES, AES, MD5, SHA-1, and SHA-256
algorithms. NXP provides an optimized C-function library that provides the appropriate
software building blocks to implement higher-level security functions.
15.2 CAU Block Diagram
A simplified block diagram is given below that illustrates the CAU and a table to show its
parts.
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 323