NXP Semiconductors K32 L2A Series, Reference Manual, Page: 691 / 1379

26.4 Functional description
Thie low-leakage wakeup unit (LLWU) module allows internal peripherals and external
input pins as a source of wakeup from low-leakage modes.
It is operational only in LLS and VLLSx modes.
The LLWU module contains pin enables for each external pin and internal module. For
each external pin, the user can disable or select the edge type for the wakeup with the
following options:
• Falling-edge
• Rising-edge
• Either-edge
When an external pin is enabled as a wakeup source, the pin must be configured as an
input pin.
The LLWU implements optional 3-cycle glitch filters, based on the LPO clock. A
detected external pin is required to remain asserted until the enabled glitch filter times
out. Additional latency of up to 2 cycles is due to synchronization, which results in a total
of up to 5 cycles of delay before the detect circuit alerts the system to the wakeup or reset
event when the filter function is enabled. Four wakeup detect filters are available for
selected external pins. Glitch filtering is not provided on the internal modules.
For internal module interrupts, the WUMEx bit enables the associated module interrupt
as a wakeup source.
For internal module DMA requests, the WUDEx bit enables the associated module DMA
request as a temporary wakeup source.
26.4.1 LLS mode
Wakeup events triggered from either an external pin input or an internal module interrupt,
result in a CPU interrupt flow to begin user code execution.
Wakeup events triggered from an internal module DMA request, result in a temporary
wake-up from LLS with CPU remaining clock gated to allow the DMA request to be
serviced. After the DMA request to the LLWU negates, the system will re-enter LLS
mode.
Chapter 26 Low-Leakage Wakeup Unit (LLWU)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 691