NXP Semiconductors K32 L2A Series, Reference Manual, Page: 464 / 1379

be processed every 11.5 cycles (4 + (4+5)/2 + 3). This is the time from Cycle 4 to Cycle x
+5. The resulting peak request rate, as a function of the system frequency, is shown in the
following table.
Table 20-6. eDMA peak request rate (MReq/sec)
System frequency (MHz)
Request rate
with zero wait states
Request rate
with wait states
48.0 5.3 4.2
66.6 7.4 5.8
83.3 9.2 7.2
100.0 11.1 8.7
133.3 14.8 11.6
150.0 16.6 13.0
A general formula to compute the peak request rate with overlapping requests is:
PEAKreq = freq / [ entry + (1 + read_ws) + (1 + write_ws) + exit ]
where:
Table 20-7. Peak request formula operands
Operand Description
PEAKreq Peak request rate
freq System frequency
entry Channel startup (4 cycles)
read_ws Wait states seen during the system bus read data phase
write_ws Wait states seen during the system bus write data phase
exit Channel shutdown (3 cycles)
20.4.4.3 eDMA performance example
Consider a system with the following characteristics:
• Internal SRAM can be accessed with one wait-state when viewed from the system
bus data phase
• All internal peripheral bus reads require two wait-states, and internal peripheral bus
writes three wait-states viewed from the system bus data phase
• System operates at 150 MHz
For an SRAM to internal peripheral bus transfer,
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
464 NXP Semiconductors