NXP Semiconductors K32 L2A Series, Reference Manual, Page: 696 / 1379

Table 27-1. Chip modes supported by the LPI2C module
Chip mode LPI2C Operation
Run Normal operation
Stop/Wait Can continue operating provided the Doze Enable bit (MCR[DOZEN]) is set and
the LPI2C is using an external or internal clock source which remains operating
during stop/wait modes.
Low Leakage Stop The Doze Enable (MCR[DOZEN]) bit is ignored and the LPI2C will wait for the
current transfer to complete any pending operation before acknowledging low
leakage mode entry.
Debug Can continue operating provided the Debug Enable bit (MCR[DBGEN]) is set.
27.1.5 Signal Descriptions
Signal Description I/O
SCL LPI2C clock line. In 4-wire mode, this is
the SCL input pin. I/O
SDA LPI2C data line. In 4-wire mode, this is
the SDA input pin. I/O
HREQ Host request, can initiate an LPI2C
master transfer if asserted and the I2C
bus is idle. I
SCLS Secondary I2C clock line. In 4-wire
mode, this is the SCL output pin. If
LPI2C master/slave are configured to
use separate pins, this the LPI2C slave
SCL pin. I/O
SDAS Secondary I2C data line. In 4-wire mode,
this is the SDA output pin. If LPI2C
master/slave are configured to use
separate pins, this the LPI2C slave SDA
pin. I/O
Memory Map and Registers
LPI2C memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4004_2000 Version ID Register (LPI2C2_VERID) 32 R See section 27.2.1/700
4004_2004 Parameter Register (LPI2C2_PARAM) 32 R See section 27.2.2/701
4004_2010 Master Control Register (LPI2C2_MCR) 32 R/W 0000_0000h 27.2.3/702
Table continues on the next page...
27.2
Memory Map and Registers
K32 L2A Reference Manual, Rev. 2, 01/2020
696 NXP Semiconductors