NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1122 / 1379

Low-
Leakage
Wakeup
(LLWU)
Reset
Control
Module
(RCM)
System
Mode
Controller
(SMC)
LP exit
CPU
LP exit
Bus masters low power bus (non-CPU)
Bus slaves low power bus
Stop/Wait
CCM low power bus
MCG enable
PMC low power bus
Flash low power bus
Clock
Control
Module
(CCM)
Flash
Memory
Module
System
Clocks
(MCG)
System
Power
(PMC)
Figure 44-2. Low-power system components and connections
44.4.2.1 Stop mode entry sequence
Entry into a low-power stop mode (Stop, VLPS, LLS, VLLSx) is initiated by a CPU
executing the WFI instruction. After the instruction is executed, the following sequence
occurs:
1. The CPU clock is gated off immediately.
2. Requests are made to all non-CPU bus masters to enter Stop mode.
3. After all masters have acknowledged they are ready to enter Stop mode, requests are
made to all bus slaves to enter Stop mode.
4. After all slaves have acknowledged they are ready to enter Stop mode, all system and
bus clocks are gated off.
5. Clock generators are disabled in the SCG unless configured to be enabled in Stop
mode. See the SCG module information for the programming options.
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
1122 NXP Semiconductors