NXP Semiconductors K32 L2A Series, Reference Manual, Page: 324 / 1379

Control Address Data 0
1
2
3
Control
logic
CAU_STR
4 9 32
PADDR
PWDATA
&
CMD
GO
15
PRDATA
OP1
32
32
RESULT
CAU
CAU
Translator
4-entry FIFO
Private Peripheral Bus (PPB)
32
32 32 32
Figure 15-1. CAU block diagram
Table 15-1. CAU parts table
Item Description
Translator submodule
Provides the bridge between the PPB interface and the CAU module. Passes memory-mapped
commands and data on the PPB to/from the CAU
4-entry FIFO
Contains commands and input operands and the associated control captured from the PPB and
sent to the CAU
CAU
3-terminal block with a command and optional input operand and a result bus. More details in
following figure.
The following figure shows the CAU block in more detail.
CAU Block Diagram
K32 L2A Reference Manual, Rev. 2, 01/2020
324 NXP Semiconductors