NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1149 / 1379

TPMx_CnSC field descriptions (continued)
Field Description
Set by hardware when an event occurs on the channel. CHF is cleared by writing a 1 to the CHF bit.
Writing a 0 to CHF has no effect.
If another event occurs between the CHF sets and the write operation, the write operation has no effect;
therefore, CHF remains set indicating another event has occurred. In this case a CHF interrupt request is
not lost due to the delay in clearing the previous CHF.
0 No channel event has occurred.
1 A channel event has occurred.
6
CHIE
Channel Interrupt Enable
Enables channel interrupts.
0 Disable channel interrupts.
1 Enable channel interrupts.
5
MSB
Channel Mode Select
Used for further selections in the channel logic. Its functionality is dependent on the channel mode. When
a channel is disabled, this field will not change state until acknowledged in the TPM counter clock domain.
4
MSA
Channel Mode Select
Used for further selections in the channel logic. Its functionality is dependent on the channel mode. When
a channel is disabled, this field will not change state until acknowledged in the TPM counter clock domain.
3
ELSB
Edge or Level Select
The functionality of ELSB and ELSA depends on the channel mode. When a channel is disabled, this field
will not change state until acknowledged in the TPM counter clock domain.
2
ELSA
Edge or Level Select
The functionality of ELSB and ELSA depends on the channel mode. When a channel is disabled, this field
will not change state until acknowledged in the TPM counter clock domain.
1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
DMA
DMA Enable
Enables DMA transfers for the channel.
0 Disable DMA transfers.
1 Enable DMA transfers.
46.3.9 Channel (n) Value (TPMx_CnV)
These registers contain the captured TPM counter value for the input modes or the match
value for the output modes.
In input capture mode, any write to a CnV register is ignored.
In compare modes, writing to a CnV register latches the value into a buffer. A CnV
register is updated with the value of its write buffer according to
CnV Register Update .
Additional writes to the CnV write buffer are ignored until the register has been updated.
Chapter 46 Timer/PWM Module (TPM)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1149