NXP Semiconductors K32 L2A Series, Reference Manual, Page: 565 / 1379

22.2.1.25.2 Function
.
22.2.1.25.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SHIFTBUFNIS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SHIFTBUFNIS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.2.1.25.4 Fields
Field Function
31-0
SHIFTBUFNIS
Shift Buffer
Alias to SHIFTBUF register, except reads/writes to this register are nibble swapped. Reads return
{ SHIFTBUF[3:0], SHIFTBUF[7:4], SHIFTBUF[11:8], SHIFTBUF[15:12], SHIFTBUF[19:16],
SHIFTBUF[23:20], SHIFTBUF[27:24], SHIFTBUF[31:28] }.
22.3 Functional description
22.3.1 Shifter operation
Shifters are responsible for buffering and shifting data into or out of the FlexIO. The
timing of shift, load and store events are controlled by the Timer assigned to the Shifter
via the SHIFTCTL[TIMSEL] register. The Shifters are designed to support either DMA,
interrupt or polled operation. The following block diagram provides a detailed view of
the Shifter microarchitecture.
Chapter 22 Flexible I/O (FlexIO)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 565