NXP Semiconductors K32 L2A Series, Reference Manual, Page: 734 / 1379

When the LPI2C master is disabled (either due to MCR[MEN] being clear or
automatically due to mode entry), the LPI2C will continue to empty the transmit FIFO
until a STOP condition is transmitted. However, it will no longer stall the I2C bus
waiting for the transmit or receive FIFO and once the transmit FIFO is empty it will
generate a STOP condition automatically.
The LPI2C master can stall the I2C bus under certain conditions, this will result in SCL
pulled low continuously on the first bit of a byte until the condition is removed:
• LPI2C master is enabled and busy, transmit FIFO is empty, and
MCFGR1[AUTOSTOP] is clear.
• LPI2C master is enabled and receiving data, receive data is not being discarded (due
to command or receive data match), and receive FIFO is full.
27.3.2.3 Receive FIFO and Data Match
The receive FIFO is used to store receive data during master-receiver transfers. Receive
data can also be configured to discard receive data instead of storing in the receive FIFO,
this is configured by the command word in the transmit FIFO.
Receive data supports a receive data match function that can match received data against
one of two bytes or against a masked data byte. The data match function can also be
configured to compare only the first one or two received data words since the last
(repeated) START condition. Receive data that is already discarded due to the command
word cannot cause the data match to set and will delay the match on first received data
word until after the discarded data is received. The receiver match function can also be
configured to discard all receive data until a data match is detected, using the
MCFGR0[RDMO] control bit. When clearing the MCFGR0[RDMO] control bit
following a data match, clear MCFGR0[RDMO] before clearing MSR[DMF] to allow all
subsequent data to be received.
27.3.2.4 Timing Parameters
The following timing parameters can be configured by the LPI2C master. Parameters are
configured separately for high speed mode (MCCR1) and other modes (MCCR0). This
allows the high speed mode master code to be sent using the regular timing parameters
and then switch to the high speed mode timing (following a repeated START) until the
next STOP condition.
The LPI2C master timing parameters in LPI2C functional clock cycles are configured as
follows. They must be configured to meet the I2C timing specification for the required
mode.
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
734 NXP Semiconductors