NXP Semiconductors K32 L2A Series, Reference Manual, Page: 551 / 1379

22.2.1.15.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
PWIDTH
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
INSR
C
0 0
SSTOP
0
SSTART
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
22.2.1.15.4 Fields
Field Function
31-21
—
20-16
PWIDTH
Parallel Width
For all Shifters, this register field configures the number of bits to be shifted on each Shift clock as
follows:
1-bit shift for PWIDTH=0
4-bit shift for PWIDTH=1...3
8-bit shift for PWIDTH=4...7
16-bit shift for PWIDTH=8...15
32-bit shift for PWIDTH=16...31
For Shifters which support parallel transmit (SHIFTER0, SHIFTER4) or parallel receive (SHIFTER3,
SHIFTER7), this register field, together with SHIFTCTL[PINSEL], also selects the pins to be driven or
sampled on each Shift clock as follows:
FXIO_D[PWIDTH]:FXIO_D[PINSEL]
For SMOD=State, this field is used to disable state outputs. See 'State Mode' section for more detail.
15-9
—
8
INSRC
Input Source
Selects the input source for the shifter.
0b - Pin
1b - Shifter N+1 Output
7
—
6
—
5-4 Shifter Stop bit
Table continues on the next page...
Chapter 22 Flexible I/O (FlexIO)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 551