NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1165 / 1379

TOF bit
... ...
0
1 1 1 2 2
3 3
4 4 5 5
0 0
previous value
previous value
channel (n) output
counter
overflow
counter
overflow
counter
overflow
channel (n)
match
channel (n)
match
CNT
MOD = 0x0005
CnV = 0x0003
CHnF bit
Figure 46-6. Example of the output compare mode when the match toggles the channel
output
TOF bit
... ... 0 1 1 1 2 2 3 3 4 4 5 5 0 0
previous value
previous value
channel (n) output
counter
overflow
counter
overflow
counter
overflow
channel (n)
match
channel (n)
match
CNT
MOD = 0x0005
CnV = 0x0003
CHnF bit
Figure 46-7. Example of the output compare mode when the match clears the channel
output
channel (n) output
CHnF bit
TOF bit
CNT
MOD = 0x0005
CnV = 0x0003
counter
overflow
channel (n)
match
counter
overflow
channel (n)
match
counter
overflow
... 0 1 2 3 4 5 0 1 2 3 4 5 0 1 ...
previous value
previous value
Figure 46-8. Example of the output compare mode when the match sets the channel
output
It is possible to use the output compare mode with (ELSnB:ELSnA = 0:0). In this case,
when the counter reaches the value in the CnV register, the CHnF bit is set and the
channel (n) interrupt is generated (if CHnIE = 1), however the channel (n) output is not
modified and controlled by TPM.
46.4.6 Edge-Aligned PWM (EPWM) Mode
The edge-aligned mode is selected when (CPWMS = 0), and (MSnB:MSnA = 1:0).
Chapter 46 Timer/PWM Module (TPM)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1165