NXP Semiconductors K32 L2A Series, Reference Manual, Page: 333 / 1379

• Any CAU reference using a non-0-modulo-4 byte address (addr[1:0] ≠ 00) generates
an error termination.
• For CAU writes:
• Only the first 64 bytes of the 2-KB direct write address space can be referenced.
Attempting to access regions beyond the first 64 bytes terminates with an error.
• The second 2-KB space defines the indirect address-as-command region and any
reference in this space is allowed by the CAU.
NOTE
The CAU contains error logic to detect any illegal
command sent to it. Accordingly, there are address
values in this upper 2-KB region of the address space
that are passed to the CAU, and then detected as illegal
commands. If the CAU detects an illegal command, it
sets the CASR[IC] flag and performs no operation.
• For CAU reads:
• Any attempted read from the first 2-KB region of the address space (an
attempted direct read) is illegal and produces an error termination.
• Within the second 2-KB region of the address space, i.e., addr[11] = 1, only a
64-byte space is treated as a legal CAU store operation. The allowable addresses
are defined as:
addr[11:0] = 1000_10xx_xx_00
where the 4-bit xxxx value specifies the CAU register number. The CAU
supports a subset of the allowable register numbers, 0x0 - 0xA. Attempting a
store of a reserved register produces an undefined result.
15.6.2.2 Data integrity checks
Direct writes can send 1, 2, or 3 commands to the CAU in a single 32-bit transfer. As
shown in
Figure 15-4 , the commands include a valid bit located at bits 31, 20, and 9 of
the write data where:
• Bit 31 is the valid bit for the first command
• Bit 20 is the valid bit for the second command
• Bit 9 is the valid bit for the third command
The direct write data check validates the combination of these three valid bits. The
following table presents the three legal states associated with these bits:
Chapter 15 Cryptographic Acceleration Unit (CAU)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 333