NXP Semiconductors K32 L2A Series, Reference Manual, Page: 755 / 1379

LPITx_CLRTEN field descriptions (continued)
Field Description
Writing a '1' to this bit will disable the timer channel 1. This bit can be used in addition to T_EN bit in
TCTRL1 register. Writing a 1 will not enable the counter. This bit is self clearing and will always read 0.
0 No Action
1 Clear T_EN bit for Timer Channel 1
0
CLR_T_EN_0
Clear Timer 0 Enable
Writing a '1' to this bit will disable the timer channel 0. This bit can be used in addition to T_EN bit in
TCTRL0 register. Writing a 1 will not enable the counter. This bit is self clearing and will always read 0.
0 No action
1 Clear T_EN bit for Timer Channel 0
28.3.8 Timer Value Register (LPITx_TVALn)
In compare modes, these registers select the timeout period for the timer channels. In
capture modes, these registers are loaded with the value of the counter when the trigger
asserts.
Address: 4003_0000h base + 20h (16d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TMR_VAL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPITx_TVALn field descriptions
Field Description
TMR_VAL Timer Value
In compare modes, sets the timer channel start value. The timer will count down until it reaches 0, then it
will generate an interrupt and load this register value again. Writing a new value to this register will not
restart the timer channel; instead the value will be loaded after the timer expires. To abort the current cycle
and start a timer period with the new value, the timer channel must be disabled and enabled again.
In capture modes, this register stores the inverse of the counter whenever the trigger asserts.
0 Invalid load value in compare modes
>0 Value to be loaded (Compare Mode) or Value of Timer (Capture Mode)
Chapter 28 Low Power Interrupt Timer (LPIT)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 755