NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1288 / 1379

50.2.1 Time Stamp Timer Register Low (TSTMRx_L)
The Time Stamp Timer is a 56-bit clock cycle counter, reset by system reset. It is
readable by way of the TSTMRH and TSTMRL registers. Only 32-bit read accesses are
allowed. Any other access will generate a transfer error.
Address: 4007_50F0h base + 0h offset = 4007_50F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
VALUE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TSTMRx_L field descriptions
Field Description
VALUE Time Stamp Timer Low
Lower 32 bits of the 56-bit time stamp value. The software must read the TSTMR_L first, followed by a
read to TSTMR_H to retrieve the complete value. The all-zero reset value may not be readable because
the value will increment before it can be read by the software.
50.2.2 Time Stamp Timer Register High (TSTMRx_H)
The Time Stamp Timer is a 56-bit counters clock cycle counter, reset by system reset. It
is readable by way of the TSTMR_H and TSTMR_L registers. Only 32-bit read accesses
are allowed. Any other access will generate a transfer error.
Address: 4007_50F0h base + 4h offset = 4007_50F4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 VALUE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TSTMRx_H field descriptions
Field Description
31–24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
VALUE Time Stamp Timer High
Table continues on the next page...
Memory map and register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
1288 NXP Semiconductors