NXP Semiconductors K32 L2A Series, Reference Manual, Page: 663 / 1379

25.3.2 INTMUX Vectors
The INTMUX is designed so that it integrates with the standard NVIC vector table. Each
INTMUX source interrupt has a vector associated with it. These source vectors are
intended to immediately follow the NVIC vectors in the vector table pointed to by the
CPU's VTOR register. Interrupt service routine addresses can be placed in the INTMUX
source vectors, just like NVIC vectors.
The ISR for each of the INTMUX output channels should read the CHn_VEC register to
determine the highest priority active source interrupt out of those enabled for the given
channel. The CHn_VEC[VECN] bitfield returns the source interrupt number. The VECN
field starts at bit 2 of the CHn_VEC register, so reading the register as a whole will return
the VECN field multiplied by 4. This is the offset in bytes of the active source vector
from the start of the vector table (i.e., VTOR).
If multiple source interrupts become pending simultaneously on a single channel, the
CHn_VEC[VECN] field will read as the highest priority vector number. Priority of
source interrupts is determined by the source interrupt number. Lower numbers are
higher priortity, with source interrupt 0 being highest priority.
NOTE
Unlike the NVIC, the INTMUX does not latch pending source
interrupts. This means that the INTMUX output channel ISRs
must check for and handle a 0 value of the CHn_VEC register
to account for spurious interrupts.
Chapter 25 Interrupt Multiplexer (INTMUX)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 663