NXP Semiconductors K32 L2A Series, Reference Manual, Page: 46 / 1379

Table 2-1. Feature Summary (continued)
Feature Details
Package 100-pin LQFP
64-pin LQFP
Voltage range 1.71 V to 3.6 V
Temperature range (T
A
) -40°C to 105°C
Temperature range (T
J
) -40°C to 125°C
System
Central processing unit (Core) Arm Cortex M0+ core
Max. Core frequency 72 MHz
Max. Bus frequency 24 MHz
Nested vectored Interrupt
controller (NVIC0) 32 vectored interrupts
4 programmable interrupt priority levels
Interrupt Mux (INTMUX0) 32 input interrupt mux to 4 outputs assign to NVIC0
with OR and AND interrupt functionality
Direct memory access (DMA0) 8 channels
(Memory-Mapped) Divide and
Square Root module (DVSQ0) Yes
Non-maskable interrupt (NMI0) Yes
Software Watch Dog (WDOG0) Yes
Low-leakage Wakeup Unit (LLWU) external wake-up pins with digital glitch filter
and internal wake-up sources (see LLWU section for details)
Debug and Trace 2-pin serial wire debug (SWD)
[Micro trace buffers (MTB) + Data Watchpoints and Traces (DWT)]
Simple Cross Triggering Interface
Unique Identification (ID) Number 80-bit wide
AXBS Crossbar 4 Master 4 Slave crossbar
Core/DMA0/USB0
Peripheral Bridge (AIPS0) Peripheral bridge interface
Peripheral Clock Control (PCC) Peripheral Clock Control module that provides asynchronous clock options and gating
function for each peripheral
Crypto Acceleration Unit (CAU0) CAU0
Cyclic Redundancy Check module
(CRC) Yes
System Tick Timer (SYSTIK) one 24-bit counter
Cyclic Redundancy Check module
(CRC) Yes
Memory
Flash memory 512 KB flash
Random-access memory (RAM) 128 KB
Read-Only Memory (ROM) 32 KB
System Register File 32 bytes
Table continues on the next page...
Feature Summary
K32 L2A Reference Manual, Rev. 2, 01/2020
46 NXP Semiconductors