NXP Semiconductors K32 L2A Series, Reference Manual, Page: 740 / 1379

The LPI2C slave does not implement a timeout due to SCL and/or SDA being stuck low.
If this detection is required, the LPI2C master logic should be used and software can reset
the LPI2C slave when this condition is detected.
27.3.4 Interrupts and DMA Requests
The LPI2C master and slave interrupts may be combined depending on the device.
The LPI2C master and slave transmit DMA requests may be combined depending on the
device.
The LPI2C master and slave receive DMA requests may be combined depending on the
device.
27.3.4.1 Master mode
The following table illustrates the master mode sources that can generate the LPI2C
master interrupt and LPI2C master transmit/receive DMA requests.
Table 27-4. Master Interrupts and DMA Requests
Flag Description Interrupt DMA Request Low Power Wakeup
TDF Data can be written to
transmit FIFO, as
configured by
TXWATER.
Y TX Y
RDF Data can be read from
the receive FIFO, as
configured by
RXWATER.
Y RX Y
EPF Master has transmitted
Repeated START or
STOP condition.
Y N Y
SDF Master has transmitted
STOP condition.
Y N Y
NDF Master detected NACK
during address byte
when expecting ACK,
master detected ACK
during address byte
and expecting NACK,
or master detected
NACK during master-
transmitter data byte.
Y N Y
ALF Master lost arbitration
due to START/STOP
condition detected at
Y N Y
Table continues on the next page...
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
740 NXP Semiconductors