NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1199 / 1379

Table 47-2. TRGMUX Memory Map (continued)
Offset Register Width
(In bits)
Access Reset value
400A7024h TRGMUX LPSPI0 (TRGMUX_LPSPI0) 32 RW 00000000h
400A7028h TRGMUX LPSPI1 (TRGMUX_LPSPI1) 32 RW 00000000h
47.2.2.1 TRGMUX Register Descriptions
47.2.2.2 TRGMUX TPM0 (TRGMUX_TPM0)
47.2.2.2.1 Address
Register Offset
TRGMUX_TPM0 400A7008h
47.2.2.2.2 Function
TRGMUX Register
47.2.2.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
LK
Rese
rved
Reserved Reserved SEL2
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved SEL1 Reserved SEL0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
47.2.2.2.4 Fields
Field Function
31
LK
This bit shows whether the register can be written or not.
0 - Register can be written.
Table continues on the next page...
Chapter 47 Trigger MUX Control (TRGMUX)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1199