NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1260 / 1379

Field Function
1 - Same behavior as bit 0 above.
1
ENT_VAL
Same behavior as bit 0 above.
0 - Same behavior as bit 0 above.
1 - Same behavior as bit 0 above.
0
HW_ERR
Bit position that can be cleared if corresponding bit of TRNG0_INT_STATUS has been asserted.
0 - Corresponding bit of TRNG0_INT_STATUS cleared.
1 - Corresponding bit of TRNG0_INT_STATUS active.
48.1.3.3.39 TRNG0 Mask (TRNG0_INT_MASK)
48.1.3.3.39.1 Address
Register Offset
TRNG0_INT_MASK 400A50A8h
48.1.3.3.39.2 Function
The TRNG0 Interrupt Mask Register is a read/write register used to disable/mask the
status reporting of the (currently) three important interrupts that are generated by the
TRNG. See TRNG0_INT_STATUS register description above. Each interrupt can be
masked/disabled by de-asserting the corresponding bit in the TRNG0_INT_MASK
register. Only setting this bit high will re-enable the interrupt in the status register. Even
if the interrupt is cleared or masked, interrupt status information can be read from the
TRNG0_MCTL register.
48.1.3.3.39.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
FRQ_CT_FAIL
ENT_
VAL
HW_
ERR
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Standalone True Random Number Generator (SA-TRNG).
K32 L2A Reference Manual, Rev. 2, 01/2020
1260 NXP Semiconductors