NXP Semiconductors K32 L2A Series, Reference Manual, Page: 583 / 1379

Table 22-11. I2C Master Configuration
Register Value Comments
SHIFTCFGn 0x0000_0032 Start bit enabled (logic 0) and stop bit
enabled (logic 1).
SHIFTCTLn 0x0101_0082 Configure transmit using Timer 1 on
rising edge of clock with inverted output
enable (open drain output) on Pin 0.
SHIFTCFG(n+1) 0x0000_0020 Start bit disabled and stop bit enabled
(logic 0) for ACK/NACK detection.
SHIFTCTL(n+1) 0x0180_0001 Configure receive using Timer 1 on
falling edge of clock with input data on
Pin 0.
TIMCMPn 0x0000_2501 Configure 2 word transfer with baud rate
of divide by 4 of the FlexIO clock. Set
TIMCMP[15:8] = (number of words x 18)
+ 1. Set TIMCMP[7:0] = (baud rate
divider / 2) - 1.
TIMCFGn 0x0102_2222 Configure start bit, stop bit, enable on
trigger high, disable on compare, reset if
output equals pin. Initial clock state is
logic 0 and is not affected by reset.
TIMCTLn 0x01C1_0101 Configure dual 8-bit counter using Pin 1
output enable (SCL open drain), with
Shifter 0 flag as the inverted trigger.
TIMCMP(n+1) 0x0000_000F Configure 8-bit transfer. Set
TIMCMP[15:0] = (number of bits x 2) - 1.
TIMCFG(n+1) 0x0020_1112 Enable when Timer 0 is enabled, disable
when Timer 0 is disabled, enable start
bit and stop bit at end of each word,
decrement on pin input.
TIMCTL(n+1) 0x01C0_0183 Configure 16-bit counter using inverted
Pin 1 input (SCL).
SHIFTBUFn Data to transmit Transmit data can be written to
SHIFTBUFBBS[7:0], use the Shifter
Status Flag to indicate when data can be
written using interrupt or DMA request.
SHIFTBUF(n+1) Data to receive Received data can be read from
SHIFTBUFBIS[7:0], use the Shifter
Status Flag to indicate when data can be
read using interrupt or DMA request.
22.4.6 I2S Master
I2S master mode can be supported using two Timers, two Shifters and four Pins. One
timer is used to generate the bit clock and control the shifters and one timer is used to
generate the frame sync. FlexIO waits for the first write to the transmit data buffer before
Chapter 22 Flexible I/O (FlexIO)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 583