NXP Semiconductors K32 L2A Series, Reference Manual, Page: 833 / 1379

LPUARTx_FIFO field descriptions (continued)
Field Description
22
RXEMPT
Receive Buffer/FIFO Empty
Asserts when there is no data in the receive FIFO/Buffer. This field does not take into account data that is
in the receive shift register.
0 Receive buffer is not empty.
1 Receive buffer is empty.
21–18
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
17
TXOF
Transmitter Buffer Overflow Flag
Indicates that more data has been written to the transmit buffer than it can hold. This field will assert
regardless of the value of TXOFE. However, an interrupt will be issued to the host only if TXOFE is set.
This flag is cleared by writing a 1.
0 No transmit buffer overflow has occurred since the last time the flag was cleared.
1 At least one transmit buffer overflow has occurred since the last time the flag was cleared.
16
RXUF
Receiver Buffer Underflow Flag
Indicates that more data has been read from the receive buffer than was present. This field will assert
regardless of the value of RXUFE. However, an interrupt will be issued to the host only if RXUFE is set.
This flag is cleared by writing a 1.
0 No receive buffer underflow has occurred since the last time the flag was cleared.
1 At least one receive buffer underflow has occurred since the last time the flag was cleared.
15
TXFLUSH
Transmit FIFO/Buffer Flush
Writing to this field causes all data that is stored in the transmit FIFO/buffer to be flushed. This does not
affect data that is in the transmit shift register.
0 No flush operation occurs.
1 All data in the transmit FIFO/Buffer is cleared out.
14
RXFLUSH
Receive FIFO/Buffer Flush
Writing to this field causes all data that is stored in the receive FIFO/buffer to be flushed. This does not
affect data that is in the receive shift register.
0 No flush operation occurs.
1 All data in the receive FIFO/buffer is cleared out.
13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12–10
RXIDEN
Receiver Idle Empty Enable
When set, enables the assertion of RDRF when the receiver is idle for a number of idle characters and the
FIFO is not empty.
000 Disable RDRF assertion due to partially filled FIFO when receiver is idle.
001 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
010 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
011 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
100 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
101 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
Table continues on the next page...
Chapter 31 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 833