NXP Semiconductors K32 L2A Series, Reference Manual, Page: 769 / 1379

29.2.3 Control Register (LPSPIx_CR)
Address: Base a 10h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0
DBGEN
DOZEN
RST MEN
W
RRF RTF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPSPIx_CR field descriptions
Field Description
31–10
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9
RRF
Reset Receive FIFO
0 No effect.
1 Receive FIFO is reset.
8
RTF
Reset Transmit FIFO
0 No effect.
1 Transmit FIFO is reset.
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
DBGEN
Debug Enable
0 Module is disabled in debug mode.
1 Module is enabled in debug mode.
2
DOZEN
Doze mode enable
Enables or disables Doze mode
Table continues on the next page...
Chapter 29 Low Power Serial Peripheral Interface (LPSPI)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 769