NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1006 / 1379

PORTx_GICHR field descriptions
Field Description
31–16
GIWD Global Interrupt Write Data
Write value that is written to all Pin Control Registers bits [31:16] that are selected by GIWE.
GIWE Global Interrupt Write Enable
Selects which Pin Control Registers (31 through 16) bits [31:16] update with the value in GIWD.
0 Corresponding Pin Control Register is not updated with the value in GPWD.
1 Corresponding Pin Control Register is updated with the value in GPWD.
38.5.6 Interrupt Status Flag Register (PORTx_ISFR)
The pin interrupt configuration is valid in all digital pin muxing modes. The Interrupt
Status Flag for each pin is also visible in the corresponding Pin Control Register, and
each flag can be cleared in either location.
Address: Base a A0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ISF
W
w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORTx_ISFR field descriptions
Field Description
ISF Interrupt Status Flag
Each bit in the field indicates the detection of the configured interrupt of the same number as the field.
0 Configured interrupt is not detected.
1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the
corresponding flag will be cleared automatically at the completion of the requested DMA transfer.
Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level
sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is
cleared.
38.5.7 Digital Filter Enable Register (PORTx_DFER)
The corresponding bit is read only for pins that do not support a digital filter. Refer to the
Chapter of Signal Multiplexing and Signal Descriptions for the pins that support digital
filter.
Memory map and register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
1006 NXP Semiconductors