NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1037 / 1379

FGPIOx_PDOR field descriptions
Field Description
PDO Port Data Output
Unimplemented pins for a particular device read as zero.
0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
40.3.2 Port Set Output Register (FGPIOx_PSOR)
This register configures whether to set the fields of the PDOR.
Address: F800_0000h base + 4h offset = F800_0004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
PTSO
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FGPIOx_PSOR field descriptions
Field Description
PTSO Port Set Output
Writing to this register will update the contents of the corresponding bit in the PDOR as follows:
0 Corresponding bit in PDORn does not change.
1 Corresponding bit in PDORn is set to logic 1.
40.3.3 Port Clear Output Register (FGPIOx_PCOR)
This register configures whether to clear the fields of PDOR.
Address: F800_0000h base + 8h offset = F800_0008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
PTCO
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FGPIOx_PCOR field descriptions
Field Description
PTCO Port Clear Output
Chapter 40 General-Purpose Input/Output (GPIO)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1037