NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1039 / 1379

40.3.6 Port Data Direction Register (FGPIOx_PDDR)
The PDDR configures the individual port pins for input or output.
Address: F800_0000h base + 14h offset = F800_0014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PDD
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FGPIOx_PDDR field descriptions
Field Description
PDD Port Data Direction
Configures individual port pins for input or output.
0 Pin is configured as general-purpose input, for the GPIO function.
1 Pin is configured as general-purpose output, for the GPIO function.
40.4 Functional description
40.4.1 General-purpose input
The logic state of each pin is available via the Port Data Input registers, provided the pin
is configured for a digital function and the corresponding Port Control and Interrupt
module is enabled.
40.4.2 General-purpose output
The logic state of each pin can be controlled via the port data output registers and port
data direction registers, provided the pin is configured for the GPIO function. The
following table depicts the conditions for a pin to be configured as input/output.
If Then
A pin is configured for the GPIO function and the
corresponding port data direction register bit is clear. The pin is configured as an input.
A pin is configured for the GPIO function and the
corresponding port data direction register bit is set. The pin is configured as an output and and the logic state of
the pin is equal to the corresponding port data output register.
Chapter 40 General-Purpose Input/Output (GPIO)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1039