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Command Reference
R&S
®
ZNL/ZNLE
568
User Manual 1178.5966.02 ─ 07
SRE register
The service request enable register SRE can be used as ENABle part of the STB if the
STB is structured according to SCPI. By analogy, the ESE can be used as the ENABle
part of the ESR.
10.4.4.1
Overview of Status Registers
The status registers of the R&S
ZNL/ZNLE are implemented as shown below.
SRE
STB
STATus:OPERation Register
PPE
IST flag
(answer to parallel poll)
& = logical AND
= logical OR
of all bits
ESE
ESR
Error Queue Output Buffer
SRQ
RQS/MSS
ESB
MAV
Power on
not used
Command error
Execution error
Device-dependent error
Query error
not used
Operation complete
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
7
6
5
4
3
2
1
0
STATus:QUEStionable Register
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
LIMit1 summary
INTegrity summary
not used
not used
not used
not used
not used
not used
not used
not used
not used
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
STATus:QUEStionable
:LIMit1 Register
not used
Limit trace no. 14
Limit trace no. 13
Limit trace no. 12
Limit trace no. 11
Limit trace no. 10
Limit trace no. 9
Limit trace no. 8
Limit trace no. 7
Limit trace no. 6
Limit trace no. 5
Limit trace no. 4
Limit trace no. 3
Limit trace no. 2
Limit trace no. 1
LIMit2 summary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
STATus:QUEStionable
:LIMit2 Register
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
Limit trace no. 16
Limit trace no. 15
not used
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
STATus:QUEStionable:INTegrity Register
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
HARDware summary
not used
not used
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
STATus:QUEStionable
:INTegrity:HARDware Register
Detector meas. time limited
Port power settings exceed limits
not used
Time grid too close
Problem conc. external power meter
not used
not used
Oven cold
Instr. temperature too high
not used
not used
not used
Receiver overload
Output power unleveled
Ref. frequency lock failure
not used
10.4.4.2
Structure of an SCPI Status Register
Each standard SCPI register consists of 5 parts which each have a width of 16 bits and
have different functions. The individual bits are independent of each other, i.e. each
hardware status is assigned a bit number which is valid for all five parts. Bit 15 (the
most significant bit) is set to zero for all parts. Thus the contents of the register parts
can be processed by the controller as positive integer.
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